Now I'll walk you through some cross models
we have for crystalline silicon photovoltaics.
I'll use this section also to highlight typical
assumptions for cross models and reiterate
some of the points already covered in the
methods section.
Here I'm showing the primary supply chain
for silicon PV.
I'm going to use this slide to briefly discuss
scoping.
You could model any or all of these stages
in different degrees of detail or you could
go even further up the silicon supply chain
and model production of ferrosilicon and metallurgical
rated silicon.
For our model, we limit it to these five stages
though we do include multiple scenarios for
polysilicon and then both mono and multi crystalline
for the other four stages.
The primary goal of our TEA here is to benchmark
costs for the industry and Department of Energy
so it can aid business and policy planning
and also give some insight into cost categories
that can help direct research.
I'm showing the typical plan size for each
of these products here because we want our
model to reflect these output scales so that
it's representative of what's being done in
the market currently.
Starting with polysilicon, our graphics team
made nice animations of the manufacturing
process for all of the other steps.
Unfortunately, I don't have one for polysilicon.
So, I'll just jump right into some of the
results.
These results are a little dated but we have
more recent results for the rest of the steps
so just keep that in mind.
Here I'm showing costs by step for polysilicon
produced in the United States using the Siemens
process which is the most common method of
polysilicon production.
You can see the first step is producing trichlorosilane
from metallurgical grade silicon or MG silicon.
As I just said, we scoped our TEA so that
we aren't doing a separate model for MG silicon.
We just use an input price for MG silicon.
In these results here, it's clear that some
steps in the production process are more expensive
than others where some have higher material
costs.
Others have higher electricity costs or equipment
costs.
So, then, the cost by step results are summed
into total costs and price estimates for a
range of scenarios.
The cost by step data for the Siemens process
shown on the last slide is summed into the
first bar on this chart.
The Siemens steps were modeled using data
from multiple China locations as well as the
United States data.
You can see the differences between the first
three bars here occur mainly in the electricity
and labor categories.
Two other polysilicon production methods were
modeled for these different locations as well,
including the hyperpure Siemens process as
well as the fluidized bed reactor process.
Once I move onto ingot production in the next
slide, it will be clear why it's important
to both model the Siemens and FBR processes.
Now I'll just review the manufacturing process
for monocrystalline silicon ingots and wafers.
The silicon feedstock is typically polysilicon
chunks manufactured via the Siemens process
and small polysilicon granules produced by
the fluidized bed reactor process to fill
in the gaps between the Siemens chunks.
These polysilicon products are loaded into
a cylindrical crucible which is then heated
so that the polysilicon melts and is then
doped.
A monocrystalline silicon seed crystal is
introduced and then rotated while pulling
upward to begin the crystal pulling process.
Pulling continues until most of the polysilicon
has crystalized into a single crystal ingot.
Some polysilicon is left in the bottom of
the crucible as it now has a higher concentration
of impurities.
The ingot is removed from the crucible and
segments are cropped off either end of the
cylinder.
The rounded exterior of the cylindrical ingot
is cropped in sections to create a pseudo
square ingot.
All the cropped sections are etched and readded
to the crucible for use in the next ingot.
The sharp corners of the pseudo square ingot
left from sawing then undergo grinding and
polishing.
The pseudo square ingot is then glued to a
glass substrate on one face.
A multiwire diamond wire saw has been used
to cut the entire ingot into wafers simultaneously.
The wafers are still glued to the glass substrate
after cutting so the glass is placed in a
chemical bath to dissolve the glue and release
the wafers.
The wafers are then cleaned, separated, and
inspected.
Here are the costs by step results for a monocrystalline
P-type wafer production.
You can see a lot of the information about
the reference design and scenario details
are listed in the title and other input data
is shown throughout the figure.
From these results, it's obvious that ingot
growth is more expensive than wafering and
it's very energy intensive.
I also want to use this slide to start talking
about the concept of yield.
You'll notice here that the wire sawing step
results in five percent of wafers breaking.
This means if you need 100 wafers, you're
actually going to have to set up production
for 105 wafers.
This will compound in later steps.
I'll come back to this number.
Here are the total costs for monocrystalline
wafer production and the estimated minimum
sustainable price.
Our wafer cost model was recently updated
to model production of M4 format wafers which
are larger than the M2 format wafers that
were previously used for the past five years
or so but the industry is now transitioning
to M4.
There are economies of scale across many cost
categories when producing, processing, and
assembling modules from larger wafers.
Now that we have wafer production modeled,
we can then proceed to cell fabrication or
cell conversion.
Here I'm showing our reference designs for
five cell types.
I'm not going to discuss all five in the interest
of time but I just want to note that these
architectures vary in terms of their wafer
polarity, efficiency, current market share,
or scale production, and other features, such
as bifaciality, which offset their TEA performance.
The PERC cell or passivated emitter and rear
cell is currently the most widely produced
cell type.
So, I'm going to briefly [Audio skips] the
PERC conversion process in the next slide.
The first step in the PERC cell conversion
process is to scan the P-type silicon wafer.
Then, any saw damage is removed.
The surface is texturized.
It goes through a pre-diffusion clean.
Then, diffusion of N-type phosphorous dopins
is completed using POCI gas.
Lasers are used to create a selective emitter.
Then, a wet chemical etch is used to remove
the layer of phosphosilicate glass that formed
during POCI diffusion.
The rear side is then planarized and then
isolated by etching phosphorous from the rear.
Next, high temperatures are used to form a
layer of silicon dioxide.
Then, aluminum oxide is deposited by plasma
enhanced chemical vapor deposition or atomic
layer deposition for surface passivation.
Next, silicon nitride is deposited by plasma
enhanced chemical vapor deposition which serves
as a front side anti-reflective coating, a
backside reflector, and overall surface passivation.
Lasers are then used to create openings in
those oxide and nitride dielectric layers
so that only contacts can be created between
silicon and the rear metal, which is about
to be added.
The next step is then to screen print silver
paste for tabbing on the rear side and aluminum
paste for a back surface field on the rear
side.
Silver paste is also used to screen print
the front side for fingers and possibly busbars.
All the screen printed pastes are then cofired.
Finally, there is an optional hydrogenation
step that can improve efficiency and passivation
or cells can proceed directly to current voltage
measurements, visual inspection, and classifying
cells into bins typically based on their efficiency
or visual features.
Here are the costs by step for the PERC conversion
process.
Again, we're showing a lot of the input data
on this figure.
You can see we've broken out metallization
material costs in gray since they represent
such a large fraction of total costs, which
is pretty typical for silicon conversion processes.
Here I want to pivot back to discussing yield
again.
When the wafers are scanned at the beginning
of this process, around .1 percent are rejected
for quality purposes.
There is a similar rejection rate through
each step of the rest of the process.
By the end of the process, about one percent
of wafers or cells are ultimately rejected.
Again, to go back to our 100 number from the
wafer yield discussion, if you need 100 cells,
you actually need to aim to produce 101 cells.
So, when before, I said you'll need to produce
105 wafers to get 100 wafers, you now need
to produce 107 wafers to get 100 cells.
You can apply this to any other material in
the process and further up the supply chain
to polysilicon production as well but I just
wanted to use wafers as a discrete example.
Now, just to provide an N-type cell example
before I move into total cell cost results,
I'll review the process flow for our silicon
heterojunction solar cell conversion, which
is the next cell type expected to gain the
most market share in the near future.
The first step in the silicon heterojunction
cell conversion process is to test the incoming
N-type wafer.
Next, any saw damage is removed and the surface
is texturized.
Then the wafer is dipped in hydrofluoric acid
to remove any oxide.
Then, hydrogenated amorphous silicon layers
are deposited on the front side by plasma
enhanced chemical vapor deposition where an
intrinsic layer is deposited first, followed
by a P-type layer.
The same is completed on the rear side where
hydrogenated amorphous silicon is deposited,
except an N-type layer is deposited after
the intrinsic layer.
Then, indium tin oxide is sputtered onto both
the front and back sides and the front and
back sides are then metallized where, notably,
the back side has periodic contact such that
the absorber is exposed.
Finally, the completed cells undergo current
voltage testing and sorted into bins.
Here are the costs by step results for the
heterojunction or SHJ cell conversion process.
Again, the metallization materials are a large
fraction of the costs and for SHJ production
that equips any other production step.
I do want to note that our cost by step analysis
shows only costs that are specific to the
cell conversion process.
So, the wafer price is not shown in these
figures.
I do want to highlight wafer pricing in the
next slide.
Here are the total costs and MSP estimates
for a few different reference designs and
scenarios.
You can see here we're comparing multiple
iterations of PERC and SHJ architectures.
The PERC rear contact can be printed to create
either monofacial or bifacial cells where
less metal is used on the back surface for
the bifacial configuration and some cost savings
occur due to decreased metal usage.
For SHJ scenarios, when comparing screen printing
versus electroplating metallization processes,
the difference in metal usage versus equipment
costs essentially cancel each other out.
When comparing screen printing of busbarless
versus busbar contact configurations, the
reduction of metal usage in the busbarless
configuration is combined with the lower equipment
costs of screen printing and results in the
lowest cost SHJ cell scenario.
It is also important to note here that the
PERC cells use P-type wafers, which are less
expensive than the N-type wafers used for
the PERL and SHJ cells shown here.
However, the wafer costs for the SHJ cells
do not appear as elevated as the PERL cell
due to the higher SHJ efficiency and using
the metric of dollars per watt.
Now we'll move to the fast age of our cost
model module assembly.
I'll review a typical monofacial PERC module
assembly process in the next slide.
The first step is the automated unloading
of AR coated solar glass where the AR side
is facing down.
An encapsulant sheet is then laid down on
top of that glass.
Strings of cells are created by automated
tabbing, stringing, and contactless infrared
soldering where the silver on the front side
of the cell is connected to the silver on
the back side of the adjacent cell.
Robotics then place these strings onto the
encapsulant sheet and string connector ribbons
are soldered.
After this, a second encapsulant sheet is
laid down on top of the strings and a back
sheet is then laid on top of the second encapsulant
sheet.
The module then proceeds through visual inspection
and electroluminescence testing.
Once it passes quality control, the module
is then laminated in a furnace.
After lamination, the edges of the module
are trimmed and an aluminum frame is fitted
and silicon sealant is applied.
Next, string connector leads are soldered
into a junction box.
A serial number is affixed to the module and
the module undergoes curing.
Finally, the module undergoes current voltage
testing and electroluminescence inspection
after which the modules are sorted into bins
based on performance.
Here are the costs by step for a monofacial
module assembly.
We've broken out most of the individual material
costs for these steps where the two largest
cost contributors are the front glass and
the aluminum frame.
It's important to note that the glass is more
expensive than the back sheet shown here,
which will be relevant when comparing monofacial
versus bifacial scenarios in the next slide.
Here we're showing total costs and MSPs for
the appropriate module configurations that
correspond to the cell scenarios we discussed
a few slides back.
Note that the module price trends do not exactly
track with the cell price trends from the
previous figure.
In this figure, bifacial PERC modules are
more expensive than the monofacial PERC modules
due to the rear sheet of glass replacing the
less expensive back sheet.
Finally, here is an example of how you can
use your cost model and TEA results to roadmap
the technology.
The left most bar here is showing the TEA
results generated a few years ago to benchmark
the industry at the time.
The next bar to the right shows our cost model
results from last year.
The data updates that resulted in the cost
changes between these two years are summarized
above in the text box.
These are mainly material cost reductions,
material usage reductions, economies of scale,
and efficiency improvements.
We then estimate what we think the next data
updates will be based on the trends we are
observing in industry to create a projection
for the coming years, including larger wafer
and ingot sizes, further material usage reductions,
as well as efficiency and throughput increases.
That concludes my silicon section review.
If you're interested in seeing more detail
on any of this, please see our most recent
publication where our silicon model results
were published in great detail.
The reference is shown here on this slide.
Now we will go through some of the thin-film
cost modeling results for CIGS, CdTe, and
III-Vs.
We're going to start with CIGS.
As you know from the earlier presenter, the
first step in technomagnetic analysis is to
establish a reference device stack that specifies
the layers and the thicknesses that are used
in the device.
For CIGS, unlike, for example, a specific
class of silicon technology, the device stacks
are a lot less standardized and there are
many different designs.
I'm showing you three on the bottom that we've
used for benchmarking in the past.
As an example, the one that I'll be walking
you through today in terms of cost is the
one on the far right with the cad sulfide
buffer layer.
When we're creating device stacks or if you
want to do this on your own, there are really
a few key things that are important to consider.
You really want to make these so that you're
benchmarking the technology and its costs
without being specific to one company and
so that you can generally inform R&D directions.
There are a few reasons why it's really important
not to try to represent one specific company.
This helps protect proprietary information.
It's really important that we maintain trust
with the manufacturers who we collect data
from and ensure that their proprietary information
is kept confidential so that we can continue
to have those relationships and collect the
data that we need for our analysis from them.
Having a more generic benchmark design also
helps avoid the appearance that you are representing
a specific company's cost or are trying to
market that company.
It also just makes the analysis more broadly
applicable with an industry in academia.
Once we've established the device stack, the
next step is to establish a reference manufacturing
process flow again as you also saw with the
other technologies.
So, now, I'll walk you through that for the
CIGS process we're analyzing here.
Now I'll walk you through the manufacturing
process flow that we use to calculate the
CIGS costs in this case.
First, unload, inspect, and wash the back
glass, which is soda lime back glass in this
case.
Then sputter the molybdenum back contact layer.
Then laser scribe through that molybdenum
back contact layer.
Next, deposit the CIGS layer itself.
In this case, we're assuming a two-step sputtering
plus batch selenization and sulfurization
process.
Then deposit the buffer layer either with
sputtering or chemical bath deposition.
Then scribe again using a mechanical scribe
through the buffer down to the molybdenum.
Then deposit the window in TCO layers using
sputtering in this case but MOCVD or other
processes could also be used.
Then scribe again down to the molybdenum and
use laser edge isolation.
Finally, electrically connect the monolithically
integrated cells by solder welding metal ribbon
busbars and connecting adhesive tape.
Then assemble the module by connecting the
busbar assembly to the front glass with the
EVA and an edge seal.
Lastly, attach the junction box, light soak,
and perform any testing, including hi-pot
testing, ground continuity, and solar simulator
J-V testing.
Then, visually inspect module, bin it, and
pack it.
Finally, I'll walk you through the other key
input assumptions we made in our model.
All these inputs are really important in calculating
costs.
If you're setting up your own model, it's
important to carefully select each of these
values and think about why you're selecting
them.
We do this based on market benchmarks, so,
where we think that the leading companies
are in terms of their capacity yield loss
and where they're manufacturing.
We also change these parameters to explore
different scenarios in terms of future directions
for technologies or to look at variability
between companies.
Here we assumed a one gigawatt per year production
capacity for the plant at a ten percent cumulative
manufacturing yield loss.
In our models, we actually have a different
yield loss for each step that's based on our
interview data.
And then, it's cumulated to determine how
much is lost at the end of the production
process.
We're assuming manufacturing in Japan, which
is where Solar Frontier, who is the leading
CIGS company in terms of their capacity, is
located.
Again, we're not trying to represent Solar
Frontier's cost with this.
It just helps us get a benchmark for where
CIGS may be generally with that location of
manufacturing.
Here's the result.
These are the step-by-step costs for CIGS.
This is based on 2019 data.
We haven't updated these results this year.
You can see a couple things that jump out
from this.
One of them is that you add up all of the
costs associated with the balance of modules,
so, things like unloading and washing the
back glasses.
Materials costs includes the cost for the
glass itself.
The front glass, bonding everything together,
the junction box, and sticker label, and the
frame actually add up to being a significant
portion of the overall costs and aren't really
related to the cell layers themselves.
Another thing that you'll notice is this selenization
and sulfurization step is very expensive.
This is because of the batch process that
we assumed, which is very slow.
Because of that, there are many tools that
are needed in parallel to meet the required
throughput.
That increases the depreciation expense as
well as the utilities and labor costs.
If you add up all of the bars from the step-by-step
chart on the previous slide, you'll get around
40 cents a watt.
That's just for the manufacturing cost.
That does not include any overhead costs or
markups.
We wanted to look and just see on a manufacturing
cost basis where could this technology potentially
go in the future if there are different improvements
made.
That's what this waterfall chart is showing
you starting at that 40 cents a watt value.
What happens if you increase the manufacturing
yield from 90 to 95 percent?
You can see that has a little bit of an effect
here.
A much larger effect could come from increasing
the throughput of manufacturing the CIGS layer.
In this case, that's the combined throughput
of sputtering the CIGS precursors as well
as the selenization and sulfurization step.
But the vast majority of the time is spent
in that batch selenization and sulfurization
process, like I mentioned.
So, it's really about speeding up that process
or finding an alternative.
There are alternatives, such as co-evaporation
or inline rapid thermal processing for selenization
and sulfurization that people have looked
at.
We have seen that those can help to improve
the throughput of these processes but are
not at the scale of the two step batch process
yet in production.
If you remove the frame, you can also save
a pretty significant amount in costs.
There are some frameless modules available
today as well.
You can see how increasing the efficiency
in different steps influences costs.
Efficiency can really be a big driver of cost
reductions as well.
Another major way that we've seen you can
decrease CIGS cost is by increasing the area
of the module.
In this case, the example is shown for a 2X
increase in module area.
If you add all of these together, you could
end up at some module with a manufacturing
cost of around 16 cents a watt DC.
Again, that's not the price you would see.
It does not include overhead and it doesn't
include any profit.
That's what you're looking at here.
Now we'll take a look at something similar
for CdTe.
This is the representative device stack that
we use for CdTe cost modeling.
We assume typical cell widths between 5.5
and 5.7 millimeters.
The CdTe layer itself is between two and three
µm.
Now I'll walk you through the process flow
that we use for NREL's CdTe cost model.
First, we deposit a transparent conducting
oxide or TCO on heat treated front glass.
Then we wash the front glass.
Then deposit a cadmium sulfide buffer layer
followed by the CdTe absorber layer and then
a cad fluoride activation.
Then we have a precontact wash and aqueous
copper diffusion step followed by a P1 laser
scribe through the cad sulfide, CdTe, and
TCO layers.
Then fill those scribes in with insulator
for cell isolation.
Then we have a second laser scribe.
Then screen print back contact metallization
paste.
Then sputter an adhesion layer and a diffusion
barrier.
Then sputter the back electrode stack.
Then have the third scribe.
This is typically a mechanical scribe down
to the CdTe followed by edge isolation.
Then we electrically connect the monolithically
integrated cells by solder welding metal ribbon
busbars and conducting adhesive tape.
Finally, assemble the module by feeding the
busbar ribbons through the predrilled hole
in the tempered back glass bonding the cells
and the busbar assembly to the EVA back glass
and edge seal.
We complete the assembly by attaching the
junction box onto the module, light soaking,
and then performing any testing, hi-pot testing,
ground continuity, and solar simulator J-V
testing and then visually inspecting the module,
binning and packing it.
Now we'll take a look at III-V solar cell
cost modeling.
There are many different III-V solar cell
device stacks as well, including variations
on cells with different numbers of junctions,
as well as just having many different cells
with single junction technology, dual junction,
or three plus junctions.
What I'm showing here is the reference device
stacks that we use for a three junction device,
which is a lattice matched device on a germanium
substrate.
Again, there are many different junction devices
and architectures that are used today but
this one is one of most common.
The dual junction device in the middle, which
is a gallium arsenide cell with gallium indium
phosphide on top and then a single junction
gallium arsenide cell.
In our benchmark case, we assume that all
these technologies have their epitaxial layers
grown via MOCVD, which is the most common
process used in the industry today.
We also assume low volumes consistent with
where the industry is today.
Currently, on the order of hundreds of kilowatts
of III-V solar cells are produced each year,
which is many orders of magnitude less than
CIGS, CdTe, and particularly silicon.
The main area where these are used is in space
applications which are less sensitive to the
cost per watt which is high for these technologies
but really need the extra performance in terms
of efficiency and weight in order to optimize
the overall cost of the space structures themselves.
First, we'll look at our results.
We'll look at the costs associated with those
single and dual junction device stacks that
I showed earlier.
In this case, we're assuming that the cells
are epitaxially lifted off of the gallium
arsenide substrate and then that the substrate
is reused five times.
This is different from the assumption that
we made in the three junction lattice matched
on germanium cell we just looked at.
That's the primary reason for the difference
in the substrate cost between those two device
stacks that I'm showing.
Currently, the yield associated with that
epitaxial lift off and reuse process is highly
uncertain and variable.
So, that's something to just take with a grain
of salt.
We made an assumption here.
You can see the details of the assumptions
that were made in our most recent publication
on this topic if you're interested.
What you can see from these results is that
even with the substrate reuse, the costs are
still pretty high.
Manufacturing costs around $40.00 a watt.
MSP is between $60.00 and $70.00 a watt for
both technologies.
The higher efficiency of the two junction
offsets is the increase in the epitaxial growth
costs associated with that because the efficiency
also helps to drive down the non-epitaxial
growth costs of the cell.
In both of these cases, you can see though
that substrate processing and epi growth all
still play an important role in driving the
costs.
The costs associated with CMP or a chemo mechanical
polish that's used during the reuse process
to reprepare the surface of the substrate
for the next growth is a very significant
cost and really limits the degree to which
you can drive down substrate costs unless
you're able to find an alternative to CMP.
Again, like any of the other technologies,
costs for specific company and prices that
that company is offering in the market which
can be separate from costs completely may
differ.
Now, I want to talk to you a little bit about
some of the challenges associated with trying
to take these estimates that we have of costs
at these very low production volumes and translate
those to a high volume to understand the potential
of these III-V technologies.
Like we mentioned before, several hundred
kilowatts a year is the current volume that
these cells are produced at.
So, going to a hundred megawatts a year would
be greater than 100X increase in production
volume.
A gigawatt per year would be greater than
1,000X increase in production volume.
So, there are a lot of assumptions and guesses
that we have to make in understanding how
these costs could scale.
Just to give you one example of that, the
current global production for gallium arsenide
wafers on a six inch equivalent basis, if
you assume a 30 percent efficiency for a cell,
is around six megawatts per year.
That's for all applications, not just solar.
Solar is actually a relatively small part
of it.
But this is including all applications of
gallium arsenide.
That means that the whole supply chain would
need to expand significantly to serve these
markets if solar cell production scaled up
to these levels.
Because of that, the cost and price are uncertain.
If we ask the manufacturer, what is this going
to cost at that volume?
They're guessing, too, because they haven't
really developed the processes to do that.
They're also not sure how that would influence
the dynamics of the input material pricing.
We try to do as good of a job of this as we
can, again, by really interviewing manufacturers
and trying to dig into what drives differences
in input material pricing.
What are the commodity prices of the input
materials?
How much of those are produced each year and
are needed to create the different components
that go into the cell manufacturing, like
the substrate?
If we do try to guesstimate what the cost
could look like scaled to the best of our
knowledge using a combination of our model,
and those interviews, and fundamental data
about pricing, and how that evolves with scale,
this is what we could get.
Again, in our most recent publication, there's
a roadmap between those very high $50.00 a
watt plus costs and this stage one bar.
If we jump ahead to a case where we're looking
at 50 megawatt per year production – which
is still very modest in terms of solar production
generally – and we assume that instead of
MOCVD we use dynamic hydride vapour phase
epitaxy for the epitaxial growth, 25 substrate
reuses with a lower cost for each chemo mechanical
polish and that you don't need to use the
CMP every reuse, only every five reuses, and
that you can electroplate lower cost metallization
as opposed to using higher cost metals and
EBM process like today, you could get around
$2.00 a watt.
Again, that assumes that a laboratory process
dynamic HVPE is scaled up successfully to
higher volumes without unanticipated costs
arising.
If you get up to the gigawatt plus production
volumes and you can get a six inch or an eight
inch substrate that's $1.00 total for everything
– that's the substrate, any cost associated
with lift off if you're still doing that,
any cost associated with the chemo mechanical
polish if you're still doing that – then
you could potentially get up into the sub
50 cent a watt or 50 cent to a dollar a watt
range.
That gives you an overview of the current
technology for these three different thin-film
materials, CIGS, CdTe, and III-Vs, and where
they may go in the future.
