Hello
In this video, I will design a VGA output circuit
I explained the signal format in the previous video
I will explain the specific timing chart
The signal starts from the yop left of the display
When one horizontal row is over, it will move to the next lower row
The signal repeats them until it reaches the bottom row
The signal then starts again from the top left
The timing when the signals do them is right
640x480 resolution is standard for VGA
So any display can support this resolution
Siglan speed for one pixel is 25.175MHz
The horizontal length of the screen is 640 pixels
The length from the screen to the horizontal sync signal H-SYNC is 16 pixels
H-SYNC length is 96 pixels
From there to the end of one line is 48 pixels
One horizontal line has a total length of 800 pixels
The period is 25.175MHz/800 and becomes 31.46875kHz
In the vertical direction as well, there is the timing of in-screen and V-SYNC
The signal should output the color data and H=SYNC and V-SYNC according to these value, and the screen should appear
Made those action into a circuit
The display side allows some frequency error, so the base clock is 25MHz
Based on that signal, the counter counts 800 in the horizontal direction and 525 in the vertical direction
The AND circuit reads the start and end timings of H-SYNC and V-SYNC from the value of the counter and switches the FF to generate those synchronization signals
Also, the same method is used to detect outside the screen
The signal stop reading the color data
By the way, the resoulution is set to 80x60 by reading the color data every 8 pixels
not enough available memory
Memory speed can't keep up
Since the controlling CPU is slow, if it is 640x480 it will take dozens of seconds just to fill the screen with white
That's why whey reduce the screen resolution
Aloso, the memory that stores screen data is called VRAM
Data woriting is alternated with reading by switching with analog switches
Vram address is 13bit, data is 8bit
The break down of color data is 3 bits for red, 3 bits for freen, and 2 bits for blue, and it is possible to express up to 256 colors
I would like to say that I will make it, but if there is a mistake in the timing, it is difficult to fix
Therefore, I will prototype this circuit on the breadboard except VRAM related
By the way, the color data is used as a test video signal by synthesizing the counter signal
Also, I forgot to buy a 25MHz crystal, so I used a 16MHz Ceralock instead
25MHz divided by 8 is 3.125MHz, and 16MHz divided by 5 is 3.2MHz so it can be substituted
This frequency error should be okay
Let's make it
Finished making
Recorded data has disappeared, I will omit the video of the production process
Sorry…
I can't help but it's a mess because there are so many jump wires
Almost invisible, but 13 logic ICs are used
I will confirm that this circuit works even with such wiring
The image was reflected
Since there are 40 hokes horizontally, the number of pixels in the horizontal dorection 80
There are 60 pixels in the vertical direction as designed
This is a success
By the way, there are black edges on the left and right because this display originally has a resolution of 16x9 and the signal has a resolution of 4x3
This is a picture taken from the top left corner of the screen
Look like there is no ficker due to noise
It seems that the upper part of the screen fits perfectly without protruding or black edges
This would mean that the signal complies with the standeard
This is the bottom right of the screen
This also fits on the screen
For the time being, I will analyze the signal and see it
This is a signal recorded by a logic analyzer
I will magnify one cycle of V-SYNC
The frequency of this is about 61Hz
This is the so-called refresh rate
In most standards this is 60Hz, but with gaming monitors it can be over 120Hz
This is an enlarged view of one cycle of H-SYNC
The frequency is about 32kHz
Since the standerd value is about 31.5kHz, this value is close
Finally, this is an enlarged view of one pixel
The frequency is 3.2MHz and the value as designed
This is 25.6MHz when multiplied by 8, which is close to the standard value of 25.125MHz
I was able to confim that the signal came out as designed
No problems are likely
With that, the trial production was successful
So in the next video I'm going to solder
That's all for this video
Thank you for watching
see you
