[MUSIC PLAYING]
MATTHEW HARRIGAN:
Today, I'm going
to share some work
we did running
quantum approximate optimization
on the Sycamore processor.
So problems in
discrete optimization
are prolific
throughout industry--
logistics, finance,
machine learning.
The possibility of quantum
enhanced optimization
has really driven
interest in the field.
In general, these problems
can be stated really
broadly as the goal
of finding an object x
from a finite set of
objects that minimizes
some cost function c of x.
Despite this historical interest
in quantum optimization,
there's always been this
lurking historical problem.
And to see what
that is, first, we
have to say that the very
basic prerequisite for quantum
optimization is that you have
to make the quantum system feel
the problem you're
trying to solve.
The quantum computer needs
to compute the cost function.
But how we do it
in practice is we
query the cost function
to phase basis states.
The historical problem is
that the physical limitations
of the device can constrain you
to particular families of cost
functions which are easy
to solve classically.
And [INAUDIBLE] certainly
have this problem.
But recent gate
model experiments
on quantum
optimization have also
fallen into the trap of
sticking to hardware native cost
functions.
And what do I mean by
hardware native cost function?
Well, we're going to focus
on discrete optimization
problems of a particular
form given by the formula you
see on the screen.
These are quadratic
binary cost functions.
All discrete
optimization problems
can be mapped to this
with some overhead.
But the two local
structure means
we can visualize the
cost function as graph.
If the cost function's
graph matches the hardware's
topology, it's very simple
to query the cost function
on a quantum device.
However, it should
come as no surprise
that these problems
are typically
not industrially relevant and
easy to solve heuristically.
So in this study, we studied
random instances, both
of these tailored
hardware grid problems,
but also prototypical computer
science problem families that
don't match the device,
namely three regular max cut
and fully connected
Sharrington-Kirkpatrick model,
SK model.
And for non-native
problem graphs,
we have to perform swaps
to move qubits around
to perform all the
desired interactions.
And we'll see the impact
of this overhead later.
So, for example, to implement
a 17-bit all to all connected
phasing unitary
for the SK model,
we repeatedly apply
this composite operation
given by the purple box, which
is composed of the two body
cost function
terms and a swap so
that we could bubble the
logical qubits past each other.
And you could sort of
puzzle this out on your own.
But if you do end rounds
of this interaction,
each pair interacts once
allowing you to implement
the full cost function.
Luckily there are
utilities in [INAUDIBLE]
to help you with these sorts
of tricks and compilation.
For this work, we use
the specific prescription
of the Quantum Approximate
Optimization Algorithm,
or QAOA.
And this prescribes repeated
alternating applications
of a problem unitary
and a driver unitary,
UC and UB, where the driver
unitary is relatively
simple single
qubit parameterized
x rotations that drive
transitions between the basis
states.
This a variation algorithm where
each layer has two parameters
also called angles,
gamma and beta.
We sample from
the quantum device
for a particular
parameter setting.
We sample bit strings,
compute how well
they solve the problem, and
then use a classical optimizer
to suggest new
parameters which improve
the quality of solutions.
So the number of layers is
given by this hyperparameter p.
So there are 2p
parameters to optimize.
For p plus 1, there are
only two parameters,
which lets us make a nice
diagnostic landscape plot
and demonstrate the ability
of a classical optimizer
to find the maximum.
So now we'll get into
showing some data.
This is for what we term
hardware grid problems
at 23 bits.
The graph is shown on the left.
In the middle, there is
a noiseless simulation
of what we expect the
landscape to look like,
where the color gives the
average quality of solutions
normalized and higher is better.
And on the right, we show
the experimental results.
In here for the
hardware grid problem,
we could see clear
agreement between
the noiseless simulation and
the experimental results.
Additionally, we initialized
a classical optimizer
from the red square in
the experimental plot.
And it was able to quickly
find the maximum and parameter
space whose
theoretical position is
shown with a blue star
and the [INAUDIBLE]..
And these world-class
results are possible due
to good hardware, particularly
very limited crosstalk
on the device.
There's a nice
developing tradition
of using these plots as a
visual representation of what's
going on.
I personally really like that.
And the previous
state-of-the-art for these
plots was shown at n equals 20.
And this is n equals 23.
We can also show our landscape
for the much more complicated
SK model here at a more modest
size of n equals 11 bits.
Again, the noise of
simulation is in the middle,
and the experiment's
on the right.
The hills and valleys
aren't as sharp as before.
But they're clearly there
and in the correct location.
The classical optimizer is
still able to climb uphill.
And this is, again, sort of
best-in-class performance
for what you'll see is
a very deep circuit.
In the previous complete
graph demonstration,
that maxes out at n equals 4.
So this is considerably larger
than anything shown before.
And to investigate this
a little more fully,
we'll move to a regime where we
compute the optimal parameters
classically so we
can just use those.
We can compare the performance
of many random instances
at a variety of problem sizes
at the circuit [INAUDIBLE]..
So this plot has the number
of qubits, AKA problem size,
on the x-axis.
The quality of solutions
on the y-axis, higher
is better, where the upper
band of square points
corresponds to
noiseless simulation.
And the lower band
of circle points
is actual data from the device.
And each problem size, we tossed
random instances of this graph.
These blue points are
hardware grid problems.
And we see an
interesting feature.
After about a problem
size of 10 or larger,
the performance
seems to level out.
This can be expected from
a simpler compilation
in the low degree
of the problem graph
but only assuming
a local error model
which requires good hardware.
And this sort of
plateauing behavior
suggests that we can likely
scale these implementations up
to arbitrarily large
sizes and still
get signal from the device.
There's a slightly
different story
when we do the same thing for
the Sharrington-Kirkpatrick
model.
This is at p equals 3.
And the square noiseless
simulation points
in the top band track with what
you'd expect for hardware grid
problems.
But the actual
implementation on the device
has a qualitatively
different behavior.
So this is p equals 3.
And at modest problem
sizes, 10 and fewer,
it still does a relatively
good job with performance
with definite signal in the
performance of the device.
But clearly, performance
degrades with problem size.
And scaling up could
prove to be a challenge.
And if you take a brief look
at the statistics reported
on the side, you could see that
the compilation overhead makes
the SK circuits much more
difficult for the same problem
size and going up to 153
layers of 2 qubit gates shown
on this plot.
Finally, we can look at how
things change versus depth.
There's this
hyperparameter p that
controls the depth of
the circuit [INAUDIBLE]..
Without noise, higher
p is always better.
That's this green light.
Noise makes it a trade-off.
It's the blue experimental data.
Experimentally for the
hardware grid problems,
we see a relatively flat
curve but peaks at p equals 3.
And, in fact, we can instead of
averaging over many instances,
we can look on a per-instance
basis and see that over 50%
of the problem studied are
maximized performance at p
equals 3.
And this is really
exciting because it's
going to be important to have
to scale this hyperparameter
p to get good quality solutions
on problems of interest.
And the previous best reported
that the performance at p
equals 2 could match
that of p equals
1 where here we show clear
improvement at height.
In summary,
diagnostic landscapes
show the device working well.
We could perform
variation optimization.
Hardware native problem
show desirable features
like an independent noise
and higher performance
for deeper circuits.
Real problems require
more compilation
which can lead to
challenges scaling up.
We think QAOA has been effective
as an unofficial benchmark
of hardware performance
on problems of interest.
And we'd love to see more
nonnative graphs being solved
and data being reported.
Thanks so much for everyone
tuning into the live stream.
And now, I'll pass it
back to [INAUDIBLE]..
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